The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to forming butting implants in transistor devices to improving short channel effects (SCE), controlling parasitic capacitance, and reducing junction leakage.
Well doping is typically utilized to avoid source/drain punchthrough problems which may occur in transistors having channel lengths that are scaled below 40 nanometers (nm). In partially depleted semiconductor-on-insulator (PDSOI) devices, for example, conventional methods have addressed junction leakage by forming doped wells beneath only the gate channel, and not the source/drain (S/D) regions. Alternatively, trench butting implants have been used to isolate gate well regions for reducing junction leakage and punchthrough.
Referring to FIGS. 1-3, a conventional semiconductor device 100 is illustrated. The conventional semiconductor device 100 includes a gate stack 102 formed on a substrate 104. According to the conventional process flow, S/D regions 106 are formed at opposing sides of a gate stack 102 using, for example, an etching process. The etching process results in wide exposed areas of the S/D region. After performing the etching process, ions are implanted in the etched S/D regions 106 to form the trench butting implant regions 108 illustrated in FIG. 3. Depositing the ions after recessing the S/D regions 106, however, creates non-uniform trench implants having increased widths (wI) due to the wide exposed areas of the etched S/D regions. The increased widths of the trench butting implants reduce the width of the gate well region.